This invention relates to an improvement applicable to semiconductor devices and methods for producing a semiconductor device. More specifically, this invention relates to an improvement applicable to static random access memories (hereinafter referred to as SRAMs) e.g. a high resistance load type SRAM and a thin film transistor (hereinafter referred to as a TFT) load type SRAM.
An SRAM is classified into a high resistance load type SRAM and a TFT load type SRAM. These SRAMs are involved with various fundamental problems to be further removed, the fundamental problems including e.g. connection of a driver transistor and a load.
A method for producing a high resistance load type SRAM will be described below.
FIGS. 1 through 7 are cross-sectional views of a semiconductor wafer illustrated for describing the process for producing a high resistance load type SRAM available in the prior art. FIGS. 8 through 13 are plan views of a semiconductor wafer corresponding to FIGS. 1 through 7. The cross section of the cross-sectional views is shown by Y--Y line illustrated in FIG. 13.
Referring to FIG. 1, the LOCOS process is conducted to produce a field insulator layer 2 having a thickness of e.g. 4,000 .ANG. on selected areas of a p.sup.- -Si substrate 1. Si.sub.3 N.sub.4 mask layer (not shown) employed for the LOCOS process is removed, and the active regions are exposed. The surface of the active region is oxidized to produce a gate insulator layer 3 having a thickness of e.g. 100 .ANG. on the active region. The gate insulator layer 3 is selectively removed to produce a contact hole 3A by conducting a wet etching process which employs hydrofluoric acid as the etchant.
Referring to FIGS. 2 and 8, a chemical vapor deposition process (hereinafter referred to as a CVD process) is conducted to produce a first poly crystalline silicon layer 4a having a thickness of e.g. 1,500 .ANG.. A gaseous phase diffusion process is conducted to introduce n-type impurities (e.g. phosphorus and arsenic) into the p.sup.- -Si substrate, and an n.sup.+ -region 5' containing n-type impurities by e.g. 1.times.10.sup.21 cm.sup.-3 is produced.
Referring to FIG. 3, a reactive ion etching process (hereinafter referred to as RIE process) is conducted to selectively pattern the first poly crystalline silicon layer 4a for the purpose to produce a gate electrode 4 which actually acts as a wire line or a gate electrode of a driver transistor. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas of the RIE process. An ion implantation process is conducted to introduce arsenic ions (n-ions) into the p.sup.- -Si substrate 1, and a source region 5 and a drain region 6 are produced.
Referring to FIG. 4 and FIG. 9, a CVD process is conducted to produce an SiO.sub.2 layer 7 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 7A for a ground line shown in FIG. 9. For this RIE process, a resist mask is employed, and a mixture of CHF.sub.3 gas and He gas is employed as the etching gas. A CVD process is conducted to produce a second poly crystalline silicon layer, having a thickness of e.g. 1,500 .ANG. which is patterned into a ground line 8 by conducting a RIE process in which a mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas.
Referring to FIGS. 5 and 10, a CVD process is conducted to produce an SiO.sub.2 layer 9 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 9A for a load resister, in the SiO.sub.2 layers 9 and 7. A mixture of CHF.sub.3 and He is employed as the etching gas for the RIE process.
Referring to FIG. 6, a CVD process is conducted to produce a third poly crystalline silicon layer having a thickness of e.g. 1,500 .ANG.. Arsenic ions (n-ions) are selectively introduced to the region which is scheduled to be the feeder of a positive power supply V.sub.cc and a region at which a high resistance load contacts with the gate electrode 4. For this ion implantation process, a resist mask is employed and a preferable dosage and a preferable acceleration energy are respectively 1.times.10.sup.15 cm.sup.-2 and 30 KeV. A RIE process is conducted to pattern the third poly crystalline silicon layer for the purposes to produce a contact part 10, a high resistance load 11 and a feeder 12 of the positive power supply V.sub.cc. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas of this RIE process.
Referring to FIGS. 7 and 11, a CVD process is conducted to produce an insulator layer 13 consisting of an SiO.sub.2 layer having a thickness of e.g. 1,000 .ANG. and a phosphosilicate glass layer having a thickness of e.g. 5,000 .ANG.. A reflow process is conducted to make the surface of the insulator layer 13 flat. A resist process and a RIE process are conducted to produce contact holes 13A for a bit line, in the insulator layer 13.
Referring to FIGS. 7 and 12, a sputtering process is conducted to produce an Al layer having a thickness of e.g. 1 micrometer, and a photolithography process is conducted to pattern the Al layer for the purpose to produce a bit line 14. The significance of the elements e.g. BL etc. which are shown in FIGS. 7 and 12 but are not discussed above will be clear, when FIG. 14 is referred to.
FIG. 13 is the plan view of a finished high resistance load type SRAM produced by the process described above, referring to FIGS. 1 through 12 and the same emblems as were employed in FIGS. 1 through 12 are employed also in FIG. 13. For the simplicity's sake, however, the bit line 14 shown in FIGS. 7 and 12 are not illustrated in FIG. 13.
FIG. 14 is an equivalent circuit of the high resistance load type SRAM produced by the process described above, referring to FIGS. 1 through 13.
Referring to FIG. 14, Q.sub.1 and Q.sub.2 indicate driver transistors, Q.sub.3 and Q.sub.4 indicate transfer gate transistors, R.sub.1 and R.sub.2 indicate high resistance load, WL indicates a word line, BL and /BL indicate bit lines, S.sub.1 and S.sub.2 indicate nodes, V.sub.cc indicates a positive power supply, and V.sub.ss indicates a negative power supply.
The function of the foregoing high resistance load type SRAM will be described below.
The positive power supply V.sub.cc is selected to be 5 V and the negative power supply V.sub.ss is selected to be 0 V. Supposing the voltage of the node S.sub.1 is 5 V and the voltage of the node S.sub.2 is 0 V, the transistor Q.sub.2 is ON and the transistor Q.sub.1 is OFF. Provided the transistor Q.sub.1 is OFF and the resistance thereof is sufficiently higher than that of the high resistance load R.sub.1, the voltage of the node S.sub.1 is kept at 5 V. On the other hand, provided the transistor Q.sub.2 is ON and the resistance thereof is sufficiently less than that of the high resistance load R.sub.2, the voltage of the node S.sub.2 is kept at 0 V.
This operation is, however, involved with a drawback wherein a DC current whose intensity is inverse proportional to the resistance of the high resistance load R.sub.2, flows from the positive power supply V.sub.cc toward the negative power supply V.sub.ss.
Since the quantity of the memory cells integrated in one chip of the foregoing high resistance load type SRAM increases following an increase in integration, the total power consumption of one chip increases, unless the power consumption of a memory cell is decreased. Therefore, the foregoing DC current is required to be decreased. To satisfy this requirement, the value of the high resistance load R.sub.2 and R.sub.1 is required to be increased. In the case where this resistance is increased, however, the potential of the node connected to the driver transistor which is then OFF, S.sub.1 in this case, can hardly be kept stable.
For the purpose to remove the foregoing drawbacks, a TFT load type SRAM was developed.
A method for producing a TFT load type SRAM will be described below.
FIGS. 15 through 23 are cross-sectional views of a semiconductor wafer illustrated for describing the process for producing a TFT load type SRAM available in the prior art. FIG. 24 is a plan view of a TFT load type SRAM. The cross section of the cross-sectional views is shown by Y--Y line illustrated in FIG. 24.
Referring to FIG. 15, the LOCOS process is conducted to produce a field insulator layer 2 having a thickness of e.g. 4,000 .ANG. on selected areas of a p.sup.- -Si substrate 1. Si.sub.3 N.sub.4 mask layers (not shown) employed for the LOCOS process are removed, and the active areas are exposed. The surface of the active area is oxidized to produce a gate insulator layer 3 having a thickness of e.g. 100 .ANG. on the active area. The gate insulator layer 3 ia selectively removed to produce a contact hole 3A by conducting a wet etching process which employs hydrofluoric acid as the etchant.
Referring to FIG. 16, a CVD process is conducted to produce a first poly crystalline silicon layer 4a having a thickness of e.g. 1,500 .ANG.. A gaseous phase diffusion process is conducted to introduce phosphorus (n-type impurities) into the p.sup.- -Si substrate, and an n.sup.+ -region 6A containing n-type impurities by e.g. 1.times.10.sup.21 cm.sup.-3 is produced.
Referring to FIG. 17, a RIE process is conducted to pattern the first poly crystalline silicon layer 4a for the purpose to produce a gate electrode 4 which actually acts as a wire line or the gate electrode of a driver transistor. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas of the RIE process. An ion implantation process is conducted to introduce arsenic ions (n-ions) into the p.sup.- -Si substrate 1, and a source region 5 and a drain region 6 are produced.
Referring to FIG. 18, a CVD process is conducted to produce an SiO.sub.2 layer 7 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 7A (See FIG. 24) for a ground line. A CVD process is conducted to produce a second poly crystalline silicon layer, which is patterned into a ground line 8 by conducting a RIE process in which a mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas.
Referring to FIG. 19, a CVD process is conducted to produce an SiO.sub.2 layer 9 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 9A in the SiO.sub.2 layers 9 and 7. For the process, a resist mask (not shown) is employed and a mixture of CHF.sub.3 and He is employed as the etching gas.
Referring to FIG. 20, a CVD process is conducted to produce a third poly crystalline silicon layer having a thickness of e.g. 1,500 .ANG.. Phosphorus ions (n-ions) are introduced in the third poly crystalline silicon layer. A preferable dosage and a preferable acceleration energy are respectively 1.times.10.sup.15 cm.sup.-2 and 20 KeV. A RIE process is conducted to pattern the third poly crystalline silicon layer to produce a gate electrodes 15 of a TFT, which acts as loads of a TFT load type SRAM. For this RIE process, a resist mask is employed, and a mixture of CCl.sub.4 and O.sub.2 is employed as the etching gas.
Referring to FIG. 21, a CVD process is conducted to produce an SiO.sub.2 layer 16 having a thickness of e.g. 300 .ANG., the SiO.sub.2 layer 16 acting as the gate insulator layer of the TFT. A drain contact hole 16A is produced by applying a wet etching process to the SiO.sub.2 layer 16.
Referring to FIG. 22, a CVD process is employed to produce a fourth poly crystalline silicon layer having a thickness of e.g. 500 .ANG.. An ion implantation process is conducted to introduce boron (n-type impurities) into the regions where sources and drains of a TFT are scheduled to be produced and where the feeder of the V.sub.cc power supply is scheduled to be produced. The ion implantation process is conducted with the dosage of 1.times.10.sup.14 cm.sup.-2 and the acceleration energy of 5 KeV. The region where the feeder of the V.sub.cc power supply is scheduled to be produced is illustrated in FIG. 24. A RIE process is conducted to pattern the fourth poly crystalline silicon layer, and the source region 17, the drain region 18 and channel region 19 of the TFT, and the feeder of the V.sub.cc power supply are produced. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas for the RIE process.
Referring to FIG. 23, a CVD process is conducted to produce an insulator layer 21 consisting of an SiO.sub.2 layer (lower layer) having a thickness of e.g. 1,000 .ANG. and a PSG layer (upper layer) having a thickness of e.g. 5,000 .ANG.. A reflow process is conducted to make the surface of the PSG layer flat. A RIE process is conducted to produce a contact hole for a bit line, on the insulator layer 21. For this RIE process, a resist mask is employed, and a mixture of CHF.sub.3 and He is employed as the etching gas. A sputtering process is conducted to produce an Al layer having a thickness of e.g. 1 micrometer. Thereafter, a photolithography process is employed to produce a bit line 22.
FIG. 24 is a plan view of a finished TFT load type SRAM produced by the process described above, referring to FIGS. 15 through 23, and the same emblems as were employed in FIGS. 15 through 23 are employed also in FIG. 24. For the simplicity's sake, however, the bit line 22 shown in FIG. 23 are not illustrated in FIG. 24.
FIG. 25 is an equivalent circuit of the TFT load type SRAM produced by the process described above, referring to FIGS. 15 through 23, and the same emblems as were employed in FIGS. 15 through 23 are employed also in FIG. 24.
Referring to FIG. 25, Q.sub.1 and Q.sub.2 indicate driver transistors, Q.sub.3 and Q.sub.4 indicate transfer gate transistors, Q.sub.5 and Q.sub.6 indicate load TFTs, WL indicates a word line, BL and /BL indicate bit lines, S.sub.1 and S.sub.2 indicate nodes, V.sub.cc indicates a positive power supply, and V.sub.ss indicates a negative power supply.
The function of the foregoing TFT load type SRAM will be described below.
The positive power supply V.sub.cc is selected to be 5 V, and the negative power supply V.sub.ss is selected to be 0 V. Supposing the voltage of the node S.sub.1 is 5 V and the voltage of the node S.sub.2 is 0 V, the transistor Q.sub.2 is ON, the transistor Q.sub.6 is OFF, the transistor Q.sub.1 is OFF and the transistor Q.sub.5 is ON. Provided the transistor Q.sub.1 is OFF and the resistance thereof is sufficiently higher than that of the transistor Q.sub.5 which is ON, the voltage of the node S.sub.1 is kept at 5 V. On the other hand, provided the transistor Q.sub.2 is ON and the resistance thereof is sufficiently less than that of the transistor Q.sub.6 which is OFF, the voltage of the node S.sub.2 is kept at 0 V.
Under the foregoing conditions, the resistance of the load transistors Q.sub.5 and Q.sub.6 varies following the memorized information. Therefore, a TFT load type SRAM is allowed to memorize information more stably than a high resistance load type SRAM. Since the channels of the load TFTs Q.sub.5 and Q.sub.6 are made of poly crystalline silicon layers and the crystal quality thereof is much worse than that of single crystalline silicon, however, the load TFTs Q.sub.5 and Q.sub.6 are inclined to allow leak current to flow, even under OFF condition. Since a leak current increases the power consumption of a memory chip, the TFTs are required to be made small in size.
FIG. 23 shows that the TFT load type SRAM described above has channels of the load TFTs below bit lines 22 made of the Al layers which is the top layer, remaining the insulator layers 21 including PSG layers therebetween.
This layer configuration allows the Al layers (the bit lines 22) to function as a gate electrode in combination with the insulator layer 21 which functions as a gate insulator layer, resultantly forming a parasitic transistor. Since the potential of the bit line 22 (the gate electrodes of the parasitic transistors) varies between 0 V (V.sub.ss) and 5 V (V.sub.cc ), the transistors Q.sub.6 which are to be OFF become almost ON, resultantly considerably increasing the leak current flowing therein.
For the purpose to remove this drawback, a double gate structure TFT load type SRAM was developed.
This double gate structure TFT load type SRAM has a fifth poly crystalline silicon layer which constitutes an upper gate electrode which have the same pattern as the third poly crystalline silicon layer namely the gate electrode 15 of the load TFT of the TFT load type SRAM described referring to FIGS. 15 through 25, the fifth poly crystalline silicon layer being arranged between the fourth poly crystalline silicon layer which constitutes the source region 17, the drain region, the channel region 19 etc. and the Al bit line 22, resultantly solving the problem.
FIGS. 26 through 28 are cross-sectional views of a semiconductor wafer illustrated for describing the process for producing a double gate structure TFT load type SRAM available in the prior art. The description for the process until the step in which the source region 17, the drain region 18, the channel region 19 of the TFT and the feeder of the V.sub.cc power supply is almost same as the description for the process for producing a TFT load type SRAM. Therefore, the following description will be limited to the steps which follow the foregoing steps.
Referring to FIG. 26, a CVD process is conducted to produce an SiO.sub.2 layer 23 having a thickness of e.g. 500 .ANG.. A RIE process is applied to the SiO.sub.2 layer 23 to produce a contact hole 23A which reaches the fourth poly crystalline silicon layer or the drain region 18 of the TFT.
Referring to FIG. 27, a CVD process is conducted to produce a fifth poly crystalline silicon layer having a thickness of e.g. 1,000 .ANG.. A thermal diffusion process is conducted to introduce phosphorus (n-type impurities) into the fifth poly crystalline Si layer. As a result, the fifth poly crystalline Si layer becomes to contain n-type impurities by e.g. 1.times.10.sup.21 cm.sup.-3. A RIE process is applied to the fifth poly crystalline Si layer to produce an upper gate electrode 24 of the TFT. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas for this RIE process.
Referring to FIG. 28, a CVD process is conducted to produce an insulator layer 25 consisting of an SiO.sub.2 layer having a thickness of e.g. 1,000 .ANG. and a PSG layer having a thickness of e.g. 5,000 .ANG.. A reflow process is conducted to make the surface of the PSG layer flat. A RIE process is applied to the insulator layer 25 to produce a contact hole for a bit line. For this RIE process, a resist mask is employed, and a mixture of CHF.sub.3 and He is employed as the etching gas. A sputtering process is conducted to produce an Al layer having a thickness of 1 micrometer. A photolithography process is applied to the Al layer to produce a bit line 26.
The foregoing TFT load type SRAM or the foregoing double gate structure TFT load type SRAM is allowed to stably function with a small power consumption, when it is produced as is designed. The process for producing either of them is, however, involved with some steps difficult to conduct as are required, including the step for connecting the drain and the gate of a driving transistor.
FIGS. 29 through 32 illustrate cross-sectional views of a semiconductor wafer, the cross-sectional views being illustrated for describing the steps for connecting the drain and the gate of the driver transistor of an SRAM and for clarifying drawbacks inevitably accompanying the foregoing steps.
Referring to FIG. 29, a field insulator layer 2 and a gate insulator layer 3 are produced on a p.sup.- -Si substrate 1 by conducting processes described above for the prior art. A photoresist layer 30 having an opening of the pattern for a contact hole. The contact hole 3A is produced by applying a wet etching process to the gate insulator layer 3, employing the photoresist mask 30. The photoresist layer 30 is removed by employing an O.sub.2 plasma etching process. During this process, the surface of the Si substrate 1 is slightly oxidized.
Referring to FIG. 30, the thin SiO.sub.2 layer produced during the O.sub.2 plasma etching process is removed, before a first poly crystalline silicon layer 4a is produced by conducting a CVD process. A gaseous phase diffusion process is conducted to introduce phosphorus (n-type impurities) into the first poly crystalline silicon layer 4a and the selected area of the top region of the Si substrate 1. As a result, n.sup.+ -region 6A is produced.
Referring to FIG. 31, a RIE process in which a resist mask is employed is applied to the first poly crystalline silicon layer 4a to pattern it, and a gate electrode 4 is produced.
During this process, the surface of the Si substrate 1 is exposed, and a recess 1A unexpectedly turns out to be produced.
Referring to FIG. 32, an n.sup.+ -source region 5 (not shown) and an n.sup.+ -drain region 6 are produced by employing an ion implantation process, by which arsenic ions are introduced into the top surface of the Si substrate 1.
The foregoing description has clarified that the prior art process is involved with two drawbacks. The one is that since an SiO.sub.2 layer unexpectedly produced during the O.sub.2 plasma etching process conducted for removing the photoresist layer 30 must be removed by employing a wet etching process, the gate insulator layer 3 is damaged. Since the gate insulator layer 3 is thin, the dielectric strength thereof is decreased. The other is that a recess 1A is unexpectedly produced on a part of the top surface of the Si substrate 1 during the RIE process conducted to produce the gate electrode 4. If the recess 1A is deep, the resistance of the path connecting the drain region 6 and the gate electrode 4 becomes large.
It is known that a protection layer of a poly crystalline silicon layer arranged to cover a gate insulator layer 3 is effective to prevent the foregoing damage and the resultant decline in dielectric strength from occurring for the gate insulator layer 3.
FIGS. 33 through 35 are cross-sectional views of a semiconductor wafer illustrated for describing the other steps for connecting the drain and the gate of the driver transistor of an SRAM and for clarifying drawbacks inevitably accompanying the foregoing steps.
Referring to FIG. 33, a field insulator layer 2 and a gate insulator layer 3 are produced on a p.sup.- -Si substrate 1 by conducting the process described above for the prior art. A protection layer 31 of a first poly crystalline silicon layer is produced on the gate insulator layer 3 by conducting a CVD process. A photoresist layer 30 has an opening of the pattern for a contact hole. A contact hole 3A is produced by conducting a RIE process conducted with assistance by the resist mask 30 and employing a mixture of CCl.sub.4 and O.sub.2 as the etching gas for Si and a wet etching process conducted employing hydrofluoric acid as the etchant for SiO.sub.2.
Referring to FIG. 34, the photoresist layer 30 is removed by conducting an O.sub.2 plasma etching process. During this process, the surface of the Si substrate 1 is slightly oxidized. The thin SiO.sub.2 layer produced during the O.sub.2 plasma etching process is removed by employing hydrofluoric acid, before a second poly crystalline silicon layer 4b is produced by conducting a CVD process. A gaseous phase diffusion process is conducted to introduce phosphorus (n-type impurities) into the second poly crystalline silicon layer 4b and the top region of the Si substrate 1. As a result, n.sup.+ -region 6A is produced.
Referring to FIG. 35, a RIE process in which a resist mask is employed is applied to the second poly crystalline silicon layer 4b and the protection layer 31 to pattern them, and a gate electrode 4 is produced.
During this process, the surface of the Si substrate 1 is exposed, and a recess 1A unexpectedly turns out to be produced. An n.sup.+ -source region (not shown) and an n.sup.+ -drain region 6 are produced by conducting an ion implantation process by which arsenic ions are introduced.
The foregoing description has clarified that the foregoing improved process wherein a protection layer 31 is arranged between the gate insulator layer 3 and the second poly crystalline silicon layer 4b, has removed a drawback wherein the gate insulator layer 3 is damaged by a wet etching process which is conducted to remove the thin SiO.sub.2 layer which was unexpectedly produced during the O.sub.2 plasma etching process which was inherently to remove the photoresist layer 30.
However, since the process for producing the gate electrode 4 is involved with two independent regions, one of which is the region from which both the first poly crystalline Si layer (the protection layer 31) and the second poly crystalline Si layer 4b are required to be removed and the other of which is the region from which the second poly crystalline Si layer 4b alone is required to be removed, the depth of the recess 1A becomes larger in the foregoing case described referring to FIGS. 33 through 35 than in the case described referring to FIGS. 29 through 32. Therefore, the resistance of the path connecting the drain region 6 and the gate electrode 4 becomes very large, and the path turns out discontinued by some chance. This is a serious drawback which can never be ignored.
Therefore, the first object of this invention is to provide a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged during the production process thereof.
The second object of this invention is to provide a semiconductor device, wherein no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the production process thereof.
The third object of this invention is to provide a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged and no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the production process thereof, the production process having less steps.
The fourth object of this invention is to provide a method for producing a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged during the process.
The fifth object of this invention is to provide a method for producing a semiconductor device, wherein no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the process.
The sixth object of this invention is to provide a method for producing a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged and no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the process.